Data path architectures are typically selected during register-transfer level (RTL) synthesis. After physical placement and routing, the selected data path architecture is usually not revisited.
The data path architecture selected by a logic synthesis tool may be suboptimal for a couple of reasons. The physical effects of a selected data path architecture are difficult to predict before placement and routing. The estimation of area usage, timing delays, and power consumption can be inaccurate without knowledge of the physical effects of the selected data path architecture. Typically after the initial physical implementation of the selected data path architecture, a logic synthesis tool does not review the data path architecture, nor does the typical logic synthesis tool rebuild and refine the data path components in the data path architecture.